----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Antti Lukats 
-- 
-- Create Date:    12:11:29 09/06/2007 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name:   Xiltendo
-- Target Devices: XC9536XL
-- Tool versions:  ISE 9.1+
--
-- Description: This is absolute minimal UART transmit only IP core for NDS Slot-2
-- resource utilization is 20 CPLD macrocells (XC9500 family)
-- Any writes to the slot-2 ROM address space go to UART transmit data register
-- there is no buffering, a write while transmit in progress will restart the transmitter
-- reading the slot-2 ROM address space will return TXEMPTY flag as D0, all other bits
-- are undefined
-- Baudrate is divided from PHI clock what must be enabled
-- 3 different baudrates are possible by choosing the clock frequency of PHI pin
-- TXD Transmitter output is mapped to XA(0) Pin 2 of the primary ext slot of
-- Xiltendo XC9572XL-VQ44 based CPLD board for NDS Slot-2
-- 
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity top is Port ( 
	-- Cart Slot
	PHI	: in  STD_LOGIC; -- Clock input 4.19 / 8.38 / 16.76
	CS   	: in  STD_LOGIC; -- ROM space Chip Select
	RD   	: in  STD_LOGIC; -- Read
	WR   	: in  STD_LOGIC; -- Write
	REQ  	: out STD_LOGIC; -- IRQ/DRQ output
	AD   	: inout  STD_LOGIC_VECTOR (7 downto 0); -- 8 bit of AD bus only !
	-- Sipsik SlotA 8 Pins = 6 IO's 
        XA	: inout  STD_LOGIC_VECTOR (5 downto 0);
	-- Sipsik SlotB 8 Pins = 6 IO's + VCC as I/O!
	XB	: inout  STD_LOGIC_VECTOR (5 downto 0);
        VCCB    : inout  STD_LOGIC
	
	);
end top;

architecture Behavioral of top is
-- UART Transmitter
signal SR: STD_LOGIC_VECTOR (9 downto 0) := "1000000000";
signal DONE : STD_LOGIC;
signal TXEMPTY : STD_LOGIC;
-- Baud Rate divider
signal CNT: STD_LOGIC_VECTOR (7 downto 0);
signal tick : STD_LOGIC;
signal bit_clk : STD_LOGIC;

begin
	--REQ <= '0';
	AD(7 downto 1) <= "ZZZZZZZ";
	AD(0) <= TXEMPTY when (CS='0' and RD='0') else 'Z';
	XA(0) <= SR(9); -- TXD
	-- DONE=1 when 8 bits are sent, also during STOP!
	DONE <= '1' when SR(8 downto 0)=X"000000000" else '0';
	process (bit_clk, WR)
	begin
		if (WR='0') then
			SR <= '0' & AD(7 downto 0) & '1'; -- Start + 8 data + stop
			TXEMPTY <= '1';
		elsif (rising_edge(bit_clk)) then
			SR(8 downto 0) <= SR(7 downto 0) & '0';
			SR(9) <= SR(8) or DONE;
			TXEMPTY <= DONE; -- Delay 1 bit clock for Transmitter EMPTY flag
		end if;
	end process;
	-------------------------------------------------
	-- Baud rate prescaler
	-- 4.19  => 9600
	-- 8.38  => 19200
	-- 16.76 => 38400
	-------------------------------------------------
	tick <= '1' when CNT=X"00" else '0';
	process (PHI, WR)
	begin
		if (WR='0') then
			CNT <= X"DA";
			bit_clk <= '1';
		elsif (rising_edge(PHI)) then
			if tick='1' then
				CNT <= X"DA"; -- 218
				bit_clk <= not bit_clk;
			else
				CNT <= CNT - "00000001";
			end if;
		end if;
	end process;
        
end Behavioral;

